Flash memory has assumed an increasingly important position in semiconductor memory technology. It provides relatively fast non-volatile rewritable memory, which is particularly attractive in mobile applications such as cell phones, portable music players, and other devices which rely upon battery power but are often turned off for extended periods. Nonetheless, flash memory chips are being economically fabricated which have a capacity of greater than a gigabit.
However, large-capacity flash memories of the desired characteristics have been accomplished by aggressively reducing the area of the memory cells, by reducing the thickness of many of the important layers, and by relying upon cells having a distinctively three-dimensional structure. The shrinkage has introduced severe requirements upon the etching process used to form the memory cell, especially the etching of the tungsten-based contact on the polysilicon control gate.
One type of floating memory cell 10 is illustrated in the cross-sectional view of FIG. 1. The cell is one of many formed over a crystalline silicon substrate 12. A cell stack 14 is formed over an area of the substrate 12 between a doped source region 16 and a similarly doped drain region 18 with a well region 20 of the opposite conductivity type under the stack 14. A thin gate oxide layer 22 overlies the substrate 12. The stack 14 is formed over the gate oxide layer 22 by depositing as initially unpatterned planar layers a first doped polysilicon layer 24, a coupling layer 26, usually referred to as the ONO (oxide-nitride-oxide) layer, as will be explained shortly, a second doped polysilicon layer 28, and a contact layer 30.
The ONO layer 26, illustrated in more detail in FIG. 2, constitutes the core of the storage element and includes a lower oxide layer 32 of silicon oxide approximately of the composition SiO2, an intermediate nitride layer 34 of silicon nitride approximately of the composition Si3N4, and an upper oxide layer 34 similarly of silicon oxide. The ONO layers 32, 34, 36 are very thin, typically in the range of 10 to 20 nm. The memory storage mechanism involves injecting electronic charge across one of the oxide layers 32, 36 into the nitride layer 34, where it is trapped and affects the voltage applied to the well region 20, hence affecting the conductivity between the source and drain regions 16, 18. The reading mechanism senses the current and hence the conductivity between the source and drain regions 16, 18 and hence the charge stored in the nitride layer 34. Whether charge has been injected into the nitride layer 34 determines the memory state of the flash memory cell 10.
The contact layer 30 is usually based on tungsten. Currently, tungsten silicide (WSi) is the most prevalent contact material, but other tungsten-based contact compositions are contemplated, for example, a multi-layer W/WN contact. Electrical contact to the upper end of the stack 14 is established through the contact layer 30.
A large number of such stacks 14 are simultaneously formed by further depositing a relatively thick nitride hard mask layer over the contact layer 30 and then applying a photoresist layer, which is photographically patterned. The hard mask layer is etched through the patterned photoresist and is then used as a robust hard mask to anisotropically etch at least part of the stack 14. After completion of etching, the hard mask is removed.
A more realistic structure of one embodiment of a flash memory array midway through formation is illustrated in the cross-sectional view of FIG. 3. In this embodiment, the first polysilicon layer 24 is first patterned into narrow ridge-shaped polysilicon cells 40 extending perpendicularly to the plane of the illustration. The ridges are covered with a thin conformal ONO layer 42, which may cover the top of the gate oxide layer 22 as well. In the interest of increased memory density, gaps or holes 44 between the cells 40 are made relatively small, for example, 40 nm. As illustrated, the structure is divided into a dense area 46 in which the cells 40 are tightly packed and an isolated (usually called iso) area 48 in which the first polysilicon layer has been removed and there are no cells 40.
A second polysilicon layer 50 is deposited to fill the gaps 44 and cover the cells 40 sufficiently to provide a gating structure. However, because of the narrow and deep gaps 44, troughs 52 form in the upper surface of the second polysilicon layer 50 overlying the gaps 44. A tungsten silicide layer 54 acting as a contact layer is deposited over the second polysilicon layer 50. Because of the need to reduce the thickness of the contact layer 54, the depth of the troughs 52 may be significant to the thickness of the planar portions of the contact overlayer 54. Thereafter, the nitride hard mask layer is deposited and photolithographically patterned into a patterned hard mask 56.
The etching of the tungsten-based contact layer 54, particularly when it is composed of WSi, has presented increasing difficulties as the lateral and vertical dimension shrink with increasingly large flash memories.